The present invention relates to a conductivity modulated MOS transistor device which is used as a power switching device.
Recently, a power MOSFET having source and channel regions which are formed by a Diffusion Self Align (DSA) method has been on the market as a power switching element. However, an element having a blocking voltage over 1000 V and sufficiently low ON-state resistance has not been realized yet. This is because if the blocking voltage is raised in an ordinary power MOSFET, the ON-state resistance will have been increased. To solve this problem, the use of a conductivity modulated (COM) FET, as the power MOSFET, is needed. As shown in FIG. 1, this COMFET comprises a p.sup.+ -type silicon substrate 1 serving as a drain region, a high resistance layer 2 of an n.sup.- -type formed on the silicon substrate 1, p-type base regions 3-1 and 3-2 and n.sup.+ -type source regions 4-1 to 4-3 which are formed on the surface of the n.sup.- -type layer 2 by a DSA method. The surface areas of the p-type regions 3-1 and 3-2 between the n.sup.- -type layer 2 and the n.sup.+ -type regions 4-1 to 4-3 act as channel regions 5-1 to 5-3. Further, a gate electrode 7-1 is formed through an insulation layer 6-1 over the n.sup.+ -type region 4-1, channel region 5-1 and a part of the n.sup.- -type region 2. A gate electrode 7-2 is formed through an insulation layer 6-2 over the surface areas of the channel regions 5-2 and 5-3 and n.sup.- -type layer 2 between the n.sup.+ -type regions 4-2 and 4-3. On the other hand, a source electrode 8-1 is formed on the n.sup.+ -type regions 4-1 and 4-2 and p-type region 3-1. A source electrode 8-2 is formed on the n.sup.+ -type region 4-3 and p-type region 3-2. A drain electrode 9 is formed on the p.sup.+ -type substrate 1.
For example, in case of forming the p-type region 3-1 and n.sup.+ -type regions 4-1 and 4-2 by the DSA method, the portion defining the outermost side in the mask used to form the p-type region 3-1 is also used as it is in order to form the n.sup.+ -type regions 4-1 and 4-2. This makes it possible to set a distance between the outermost side of the p-type region 3-1 and the outermost side of the n.sup.+ -type region 4-1 or 4-2, namely, a length of the channel region 5-1 or 5-2, to a desired value in accordance with diffusion process parameters such as diffusion time, diffusion temperature and the like.
When this COMFET is turned on, for instance, electrons flow from the n.sup.+ -type regions 4-1 and 4-2 into the n.sup.- -type layer 2 through the channel regions 5-1 and 5-2, respectively, and at the same time holes are injected from the p.sup.+ -type substrate 1 into the n.sup.- -type layer 2. Thus, a great amount of carriers are stored in the n.sup.- -type layer 2, thereby allowing the conductivity in the n.sup.- -type layer 2 to be modulated. The holes injected into the n.sup.- -type layer 2 flow into the source electrode 8-1, for instance, through the areas in the p-type region 3-1 below the n.sup.+ -type regions 4-1 and 4-2.
Although the COMFET shown in FIG. 1 has a structure similar to a thyristor, the source electrode 8-1 electrically connects the p-type region 3-1 with the n.sup.+ -type regions 4-1 and 4-2, so that this COMFET does not ordinarily operate as a thyristor.
This COMFET can be constituted so as to have sufficiently high blocking voltage and sufficiently small ON-state resistance owing to the conductivity modulation effect.
However, in this COMFET, when a large current flows into the COMFET when it is conductive, the voltage drop in the transverse direction at the p-base resistance area below the n.sup.+ -type regions 4-1 and 4-2 increases. The voltage drop acts to forwardly bias the pn junction between the p-type region 3-1 and the n.sup.+ -type region 4-1 or 4-2, so that this COMFET will have operated similarly to a thyristor. Thus, even if the voltages between the gate electrodes 7-1, 7-2 and the source electrode 8-1 are set to 0 V, a latch-up phenomenon is caused, so that the COMFET is not turned off.
To solve this problem, as shown in FIG. 2, conventionally, p.sup.+ -type regions 10-1 and 10-2 are formed by diffusing p.sup.+ -type impurities into the areas below the n.sup.+ -type regions 4-1 and 4-2 and n.sup.+ -type region 4-3. The resistance in the transverse direction in the area below the n.sup.+ -type regions 4-1 and 4-2 is reduced due to the existence of the p.sup.+ -type region 10-1. However, in this case, it is required to hold the impurity concentration in the channel regions 5-1 and 5-2 to be a low value; therefore, the diffusion in the transverse direction of the p.sup.+ -type region 10-1 must not reach the channel regions. Further, since the depth of diffusion of the p.sup.+ -type region 10-1 is great, a length of portion A of the transverse diffusion is long and the sheet resistance in the portion A cannot be made small enough as compared with that in a portion B, so that the resistance in the area from the channel region 5-1 to the source electrode 8-1 cannot be made sufficiently small. Consequently, the latch-up of the parasitic thyristor which is constituted by the regions 4-1, 3-1, 2 and 1 cannot be suppressed.